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-- Company: 
-- Engineer: 
-- 
-- Create Date:    20:17:56 10/13/2009 
-- Design Name: 
-- Module Name:    register - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity reg is
    Port ( I : in  STD_LOGIC_VECTOR (31 downto 0);
           clock : in  STD_LOGIC;
           load : in  STD_LOGIC;
           clear : in  STD_LOGIC;
           Q : out  STD_LOGIC_VECTOR (31 downto 0));
end reg;

architecture Behavioral of reg is

    signal Q_tmp: std_logic_vector(31 downto 0);

begin

    process(I, clock, load, clear)
    begin

	if clear = '0' then
            Q_tmp <= (Q_tmp'range => '0');
	elsif (clock='1' and clock'event) then
	    if load = '1' then
		Q_tmp <= I;
	    end if;
	end if;

    end process;

    Q <= Q_tmp;

end Behavioral;

